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Digital Verification Engineer CDI 100%. Vaud. Suiza
Trabajos de Programadores de aplicaciones en Suiza (Vaud)
Clasificación del trabajo: Profesionales científicos e intelectuales › Profesionales de tecnología de la información y las comunicaciones › Desarrolladores y analistas de software y multimedios › Programadores de aplicaciones.
Traducción de la profesión: Akademische Berufe › Akademische und vergleichbare Fachkräfte in der Informations- und Kommunikationstechnologie › Entwickler und Analytiker von Software und Anwendungen › Anwendungsprogrammierer.
Descripción de la oferta de trabajo:
Postulation en ligne uniquement : https://kandou.bamboohr.com/careers/250
Merci de mentionner sous source : ORP
Digital Verification Engineer
Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
Key responsibilities :
Work with Design Engineers in verification and validation of circuit designs
Prepare design verification plan based on design specifications
Plan and schedule assigned projects for timely completion
Utilize latest techniques, tools and technologies for design verification activities
Maintain design verification environment, track and close design bugs
Develop design verification methodologies and implement standard debug flows
Participate in design reviews
Your profile :
Minimum 5+ years’ experience in the semiconductor industry.
Expert in digital design verification, using standardized methodologies, i.e. UVM
Experience in simulating mixed signal designs with real-number Verilog behavioural models is highly desirable
Familiarity with SerDes is highly desirable
Experience with SystemVerilog Assertions (SVA) and formal verification is valuable
Experience in constrained random testbench development
Proven track record in verifying complex designs (preferably in high volume ASIC applications)
Experience with 3rd party VIP usage is an added bonus
Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus
Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)
Competencies :
Very good knowledge on Metric driven verification including test planning and coverage closure
Very good knowledge on simulation tools and debugging techniques
Knowledge of Cadence simulation tools is an added bonus
Good scripting techniques, regression setup and regression management
Good understanding of simulation and verification environments
Skilled in trade-offs between quality and schedule
Excellent team player with great communication skills, proactive and self-reliant
Be rigorous and have an analytical mind
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It
País del trabajo: Suiza.
Región: Vaud.
Ver 109 ofertas de trabajo en "Vaud" (Suiza).
Número de puestos: 1.
Empleador: Kandou Bus SA.
Instrucciones para solicitar:
Forma de contacto:
- Teléfono: +41 21 588 14 26
- Sitio web: https://kandou.bamboohr.com/careers/250
Oferta de trabajo obtenida del portal Eures, con fecha 14 de Agosto de 2024, y con identificador de la vacante:6d7742be-3e9b-11ef-8042-d67e1f03b567.
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